In industrial motor drive applications, an IGBT with a long short-circuit withstand time (SCSOA) is required. The withstand time represents how long the IGBT can stay functional and be turned off after encountering a motor fault condition where the IGBT conducts under full bus voltage (collector-emitter voltage). The withstand time is required for the driver to detect and locate the failure and turn off the system without further damage.
FIG. 1 depicts a short-circuit waveform with associated failure mechanisms A, B, C, and D. Failure types A, B and C are primarily due to parasitic thyristor latch-up. Type D is due to leakage current thermal runaway, which occurs a few hundred microseconds after device turn-off Most of today's IGBTs are designed to be latch-up immune with type D being the only failure mechanism limiting SCSOA. Since type D failure is thermally limited, SCSOA of today's IGBTs is thermally limited. The SCSOA of the IGBT can hence be improved by the following:
1) increase in silicon wafer thickness to increase over thermal mass; and/or
2) saturation current reduction.
FIG. 2 shows the dependence of short-circuit withstand time on bus voltage and saturation current. Note that,
1) SCSOA decreases with higher voltage;
2) SCSOA decreases with higher saturation current.
IGBT saturation current is highly dependent on the gate drive voltage as well as the overall MOS channel density. It should be noted that
1) saturation current increases with higher gate drive;
2) saturation current increases with higher channel density.
Channel density is inversely proportional to the cell pitch of the design. Where cell pitch is defined as the distance from one trench to the next. The wider the cell pitch, the lower the channel density and hence the lower the saturation current.
In today's motor drive applications, on-state saturation voltage reduction is as important as switching loss reduction. Methods to lower on-state saturation voltage drop include,
1) enhancement implant—increase in base drive electron injection efficiency;
2) deeper trenches—decrease in accumulation layer resistance at the tip of the trench;
3) wafer thinning—decrease in drift region resistance.
Large SCSOA demands wider cell pitch. Forward bias breakdown requires narrow cell pitch.
In order to achieve the desired channel density and breakdown voltage, narrow cell pitch is needed to reduce field crowding in which only a portion of the channels are conducting. One method for obtaining a desirable combination of channel density and breakdown voltage is shorting every other trench poly gate to emitter. Shorting gate to emitter eliminates gate drive completely for specific trenches, effectively reducing the overall channel density of the device while maintaining a narrow cell pitch to achieve the desired breakdown voltage. A structure using the latter method has been published in ISPSD 2006 by Mitsubishi, which has been defined as a damping trench for eliminating switching oscillations.
According to the present invention the saturation current of the IGBT is reduced in a unique manner to achieve the desired SCSOA. Specifically, according to the present invention, the threshold voltage of the channel at some of the trenches (e.g. every other trench) is increased.
In an IGBT (e.g. an N channel IGBT), P+ emitter contact regions are used to enhance parasitic thyristor latch-up. Such contact regions are formed in the base region and are higher in dosage (i.e. lower resistivity) compared to the P type base region in which the N channels are formed. A method according to the present invention allows the contact implant to contaminate some of the channel regions to increase the threshold voltage thereof For example, by decreasing contact to trench spacing in the mask used for the emitter contact implant the emitter contacts can be selectively offset and asymmetrically positioned relative to, for example, two opposing trenches. As a result, the channel region adjacent one trench can have a higher dopant concentration and thus a higher threshold voltage.